1 ps8746c 02/01/06 features ? eight pairs of differential clocks ? low skew < 50ps ? low cycle-to-cycle jitter < 50ps ? output enable for all outputs ? outputs tristate control via smbus ? power management control ? programmable pll bandwidth ? pll or fanout operation ? 3.3v operation ? packaging (pb-free & green): 48-pin ssop (v) 48-pin tssop (a) pi6c20800 description pi6c20800 is a high-speed, low-noise differential clock buffer designed to be a companion to pi6c410b. the device distributes the differential src clock from pi6c410b to eight differential pairs of clock outputs either with or without pll. the input src clock can be divided by 2 when src_div# is low. the clock outputs are controlled by input selection of src_stop#, pwrdwn# and smbus, sclk and sda. when input of either src_stop# or pwrdwn# is low, the output clocks are tristated. when pwrdwn# is low, the sda and sclk inputs must be tristated. block diagram 1:8 clock driver for intel pci express chipsets pin confguration out0 out0 # out0 out1 # out2 out2 # out3 out3 # div output control smbus controller pll pll_bw# src src# pll/bypass# src_div# sclk sda oe_inv oe [0:7] src_stop# pwrdwn# out4 out4 # out5 out5 # out6 out6 # out7 out7 # lock v dd_a v ss_a i ref lock oe_7 oe_4 out7 out7# oe_inv v dd out6 out6# oe_6 oe_5 out5 out5# v ss v dd out4 out4# pll_bw# src_stop pwrdwn# v ss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 src_div# v dd v ss src src# oe_0 oe_3 out0 out0# vss v dd out1 out1# oe_1 oe_2 out2 out2# v ss v dd out3 out3# pll/bypass# sclk sda
2 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets pin descriptions pin name type pin # descriptions src_div# input 1 3.3v lvttl input for selecting input frequency divide by 2, active low. src & src# input 4, 5 0.7v differential src input from pi6c410 clock synthesizer oe [0:7] input 6, 7, 14, 15, 35, 36, 43, 44 3.3v lvttl input for enabling outputs, active high. oe_inv input 40 3.3v lvttl input for inverting the oe, src_stop# and pwrdwn# pins. when 0 = same stage when 1 = oe[0:7], src_stop#, pwrdwn# inverted. out[0:7] & out[0:7]# output 8, 9, 12, 13, 16 17, 20, 21, 29, 30, 33, 34, 37, 38, 41, 42 0.7v differential outputs pll/bypass# input 22 3.3v lvttl input for selecting fan-out of pll operation. sclk input 23 smbus compatible sclock input sda i/o 24 smbus compatible sdata i ref input 46 external resistor connection to set the differential output current src_stop# input 27 3.3v lvttl input for src stop, active low pll_bw# input 28 3.3v lvttl input for selecting the pll bandwidth pwrdwn# input 26 3.3v lvttl input for power down operation, active low lock output 45 3.3v lvttl output, transition high when pll lock is achieved (latched output) v dd power 2, 11, 19, 31, 39 3.3v power supply for outputs v ss ground 3, 10, 18, 25, 32 ground for outputs v ss_a ground 47 ground for pll v dd_a power 48 3.3v power supply for pll serial data interface (smbus) pi6c20800 is a slave only smbus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 1 1 0 0/1 data protocol (1) 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit slave addr r/w ack register offset ack byte count = n ack data byte 0 ack data byte n - 1 ack stop bit note: 1. register offset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0.
3 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets data byte 0: control register bit descriptions type power up condition output(s) affected pin 0 src_div# 0 = divide by 2 1 = normal rw 1 = x1 out[0:7], out[0:7]# na 1 pll/bypass# 0 = fanout 1 = pll rw 1 = pll out[0:7], out[0:7]# na 2 pll bandwidth 0 = high bandwidth, 1 = low bandwidth rw 1 = low out[0:7], out[0:7]# na 3 tbd na 4 tbd na 5 tbd na 6 src_stop# 0 = driven when stopped 1 = tristate rw 0 = driven when stopped out[0:7], out[0:7]# 7 pwrdwn# 0 = driven when stopped 1 = tristate rw 0 = driven when stopped out[0:7], out[0:7]# na data byte 1: control register bit descriptions type power up condition output(s) affected pin 0 outputs enable 1 = enabled 0 = disabled rw 1 = enabled out0, out0# na 1 rw 1 = enabled out1, out1# na 2 rw 1 = enabled out2, out2# na 3 rw 1 = enabled out3, out3# na 4 rw 1 = enabled out4, out4# na 5 rw 1 = enabled out5, out5# na 6 rw 1 = enabled out6, out6# na 7 rw 1 = enabled out7, out7# na
4 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets data byte 2: control register bit descriptions type power up condition output(s) affected pin 0 allow control of outputs with assertion of src_stop# 0 = free running 1 = stopped with src_stop# rw 0 = free running out0, out0# na 1 rw 0 = free running out1, out1# na 2 rw 0 = free running out2, out2# na 3 rw 0 = free running out3, out3# na 4 rw 0 = free running out4, out4# na 5 rw 0 = free running out5, out5# na 6 rw 0 = free running out6, out6# na 7 rw 0 = free running out7, out7# na data byte 3: control register bit descriptions type power up condition output(s) affected pin 0 tbd rw 1 rw 2 rw 3 rw 4 rw 5 rw 6 rw 7 rw data byte 4: pericom id register bit descriptions type power up condition output(s) affected pin 0 pericom id r 0 na na 1 r 0 na na 2 r 0 na na 3 r 0 na na 4 r 0 na na 5 r 1 na na 6 r 0 na na 7 r 0 na na
5 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets functionality pwrdwn# out out# src_stop# out out# 1 normal normal 1 normal normal 0 i ref 2 or float low 0 i ref 6 or float low power down (pwrdwn# assertion) figure 1. power down sequence power down (pwrdwn# de-assertion) figure 2. power down de-assert sequence pwrdwn# out# out pwrdwn# out out# tdrive_pwrdwn# <300us, 200mv tstabl e <1ms
6 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets current-mode output buffer characteristics of out[0:7], out[0:7]# figure 9. simplifed diagram of current-mode output buffer differential clock buffer characteristics symbol minimum maximum r o 3000? n/a r os unspecifed unspecifed v out n/a 850mv current accuracy symbol conditions confguration load min. max. i out v dd = 3.30 5% r ref = 475? 1% i ref = 2.32ma nominal test load for given confguration -12% i nominal +12% i nominal note: 1. i nominal refers to the expected current based on the confguration of the device. differential clock output current board target trace/term z reference r, iref = v dd /(3xrr) output current v oh @ z 100? (100? differential 15% coupling ratio) r ref = 475? 1%, i ref = 2.32ma i oh = 6 x i ref 0.7v @ 50 0v i out 0.85v slope 1/rs r o r os v out = 0.85v max iout v dd (3.3v 5%)
7 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets absolute maximum ratings (1) (over operating free-air temperature range) symbol parameters min. max. units v dd_a 3.3v core supply voltage -0.5 4.6 v v dd 3.3v i/o supply voltage -0.5 4.6 v ih input high voltage 4.6 v il input low voltage -0.5 ts storage temperature -65 150 c v esd esd protection 2000 v note: 1. stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. dc electrical characteristics (v dd = 3.35%, v dd_a = 3.35%) symbol parameters condition min. max. units v dd_a 3.3v core supply voltage 3.135 3.465 v v dd 3.3v i/o supply voltage 3.135 3.465 v ih 3.3v input high voltage v dd 2.0 v dd + 0.3 v il 3.3v input low voltage v ss C 0.3 0.8 i ik input leakage current 0 < v in < v dd -5 +5 a v oh 3.3v output high voltage i oh = -1ma 2.4 v v ol 3.3v output low voltage i ol = 1ma 0.4 i oh output high current i oh = 6 x i ref , i ref = 2.32ma 12.2 ma 15.6 c in logic input pin capacitance 1.5 5 pf c out output pin capacitance 6 l pin pin inductance 7 nh i dd power supply current v dd = 3.465v, f cpu = 200mhz 250 ma i ss power down current driven outputs 60 i ss power down current tristate outputs 12 t a ambient temperature 0 70 c
8 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets ac switching characteristics (1,2,3) (v dd = 3.35%, v dd_a = 3.35%) symbol parameters min max. units notes t rise / t fall rise and fall time (measured between 0.175v to 0.525v) 175 700 ps 2 t rise / t fall rise and fall time variation 125 2 t skew output-to-output skew 50 ps 3 v high voltage high 660 850 mv 2 v ovs max. voltage 1150 v uds min. voltage -300 v low voltage low -150 +150 2 v cross absolute crossing poing voltages 250 550 2 v cross total variation of v cross over all edges 140 2 t dc duty cycle 45 55 % 3 t jcyc-cyc jitter, cycle-to-cycle (pll mode, measurement for differential waveform) 50 ps jitter, cycle-to-cycle (bypass mode as additive jitter) notes: 1. test confguration is r s = 33.2?, rp = 49.9?, and 2pf. 2. measurement taken from single ended waveform. 3. measurement taken from differential waveform. confguration test load board termination 475 ? 1% 49.9 ? 1% rp 49.9 ? 1% rp 33 ? 5% rs 33 ? 5% rs pi6c20800 tla tlb out out# 2pf 5% 2pf 5%
9 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets packaging mechanical: 48-pin ssop (v) packaging mechanical: 48-pin tssop (a) .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc 0.20 0.51 1.01 0.25 0.381 0.635 .008 .008 .016 0-8? 0.20 0.40 .110 2.79 .010 gauge plane .02 .04 .015 .025 x 45? .025 bsc 0.635 .291 .299 x.xx x.xx denotes dimensions in millimeters 7.39 7.59 .395 .420 10.03 10.67 .620 .630 15.75 16.00 .008 .0135 0.20 0.34 1 48 nom. max
1 0 ps8746c 02/01/06 pi6c20800 1:8 clock driver for intel pci express chipsets ordering information (1,2) ordering code package code package description pi6c20800ve ve 48-pin, 300-mil wide, ssop, pb-free and green PI6C20800AE ae 48-pin, 240-mil wide, tssop, pb-free and green notes: 1. thermal characteristics can be found on the company web site at www .pericom.com/packaging/ 2. e = pb-free and green pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com
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